This invention relates to a PLL (phase locked loop) detection circuit.
FIG. 1 is a circuit diagram showing a conventional PLL detection circuit. In FIG. 1, a predetermined signal ei is applied to one input terminal of a phase comparator 1, to the other input terminal of which the oscillation output of a VCO (voltage-controlled oscillator) 2 is applied. Thus, the phase comparator provides an output according to the difference in frequency and phase between the oscillation output and the FM input signal ei. The output of the phase comparator 1 is converted into a DC voltage by a loop filter 3. The DC voltage, after being amplified by a DC amplifier 4, becomes a detection output, and is applied, as a control voltage, to the VCO 2.
The loop filter 3, for instance, comprises: a resistor R.sub.1 is connected between the output terminal of the phase comparator 1 and the input terminal of the DC amplifier 4; and a series circuit of resistors R.sub.2 and R.sub.3 and a capacitor, which is connected between the output terminal of the resistor R.sub.1 and ground. A transistor Q.sub.0 is connected in parallel with the resistor R.sub.3. In response to a control signal V.sub.B which is produced when a turning point is substantially detected, the transistor Q.sub.0 short-circuits the resistor R.sub.3, to change the time constant of the loop filter 3, to thereby make the filter characteristic narrow and to reduce the lock-in time. In providing the PLL detection circuit in the form of an integrated circuit, the capacitor C.sub.1 is externally connected to a terminal (or a pin) A.
In the PLL detection circuit thus organized, the time constant of the loop filter 3 is changed by the switching operation of the transistor Q.sub.0. However, this method is disadvantageous in that, when the transistor Q.sub.0 is employed as the switching element, a DC offset voltage occurs which produces spike noise and makes the PLL loop unstable.